In order to make solar power a viable alternative to established generating methods such as fossil fuel and nuclear power, it is necessary to bring the manufacturing cost of solar cells down. This has been achieved to some extent in thin film devices by use of large area devices carrying small quantities of silicon. However, the efficiencies obtained for such devices are significantly lower than those obtained for silicon-wafer-based solar cell devices. In addition, the manufacturing processes currently formulated for thin film devices are still complex and require significant improvement for cost-efficient production on larger scales.
Consequently, most solar cell devices currently commercially produced are based on silicon wafer technology which has been refined to achieve commercial efficiencies in the order of 16-18%. In general, this technology involves appropriately doping the wafers to form the required p-n junctions for carrier collection. Typically, the surfaces of the wafer are passivated by dielectric layers, composed of either silicon dioxide or silicon nitride. Metal contacts can then be made to the p-type and n-type silicon in a number of different ways. Higher efficiencies have been achieved for silicon wafer solar cells where semiconductor device fabrication methods, such as photolithography, have been used to create patterned buried metal contacts in either one or both of the surfaces of the doped/passivated silicon wafer. For example, efficiencies of 24.5% and 24.7% were recorded at the University of NSW, Australia in 1999 using magnetic Czochralski (MCZ) and float-zone (FZ) silicon wafers, respectively. Both these results were obtained using photolithography and semiconductor device fabrication methods.
However, semiconductor device fabrication methods require costly equipment (e.g., lasers, mask aligners), expensive clean room environments, and generally many time-consuming steps. For example, photolithographic patterning of a dielectric layer requires deposition of a resist layer over the dielectric layer (usually by spin-coating), patterning of the resist using a prepared mask which is appropriately aligned, exposing the resist through the mask and then developing the exposed resist to form a pattern in the resist. This pattern can then be used to etch the underlying dielectric layer in the desired manner. Finally the resist layer is then removed to leave a patterned dielectric layer.
A further disadvantage of current photolithographic patterning methods is that if a number of different metal contact patterns are required, then the entire photolithographic process must typically be repeated for each pattern. For example, if it is necessary to create metal contacts to both n-type and p-type silicon, then different etching processes would be required for each contact pattern. If n-type silicon is located immediately under the dielectric, then contact to n-type can be made through holes or grooves etched in dielectric layer. Etching of dielectrics, such as silicon oxide, can be achieved using dilute hydrofluoric acid. However, making metal contact to p-type silicon from the same surface requires etching of both the dielectric layer and the n-type silicon layer located directly under the dielectric layer. Etching of silicon cannot be achieved using dilute hydrofluoric acid and therefore a different etchant must be used to etch the silicon required for the p-type contacts (e.g., “purple” etch as disclosed in WO 2005/024927). Consequently, it is difficult to use a single photolithographic process to create holes or grooves for both sets of contacts.